1. Field of the Invention
The present invention relates generally to digital signal divider circuits useful for providing an output digital signal having a frequency less than an input digital pulse or clock signal. More specifically, the present invention relates to variable, non-integer frequency division and hazard-free divider circuitry. The present invention is particularly useful in digital audio signal processing systems.
2. Brief Description of the Related Technology
In the prior art, frequency division in non-integer steps has been accomplished by utilizing combinatorial logic circuits to provide a propagation delay path for an input clock or digital pulse signal. The accuracy of such circuits was dependent upon the actual time delays realized in particular logic circuit elements. Actual delays, as distinguished from design specification, vary from one circuit to the next based upon process, the cell design, or environmental variables introduced in the manufacturing process or in use. Such prior art designs were therefore not hazard-free, and not reliable in applications requiring precision frequency division independent of process or environmental variables.